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AD9547 SYSCLK PLL stability

Question asked by GDB11 on Oct 16, 2013
Latest reply on Oct 31, 2013 by pkern



I'm currently using an AD9547 with a 10MHz OCXO as an system clock input. The problem I'm having is that the system clock will not remain stable (checking via system clock stability signal on a M pin) with the duty cycle of the OCXO I'm using (45/55). If I 'clean' the duty cycle to 50/50 using an extrenal PLL prior to the AD9547 clock input, the stability indicator shows stable.


The system clock (bypassed) duty cycle is 40/60 in the datasheet. Is there a similar figure for when using the system clock PLL? I'm using the internal loop filter. Should I switch to an extenal one? Or more simply, is there a way of setting it up so that a less than 50/50 duty cycle is acceptable?


Thanks for your help