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PPI Sync revisited (BF561)

Question asked by Laz on Jun 1, 2010
Latest reply on Jul 16, 2010 by Laz

My issue is somewhat related to this one: http://ez.analog.com/message/4518#4518

 

I am using an Aptina camera connected to the PPI0 port, using Frame and Line valid controls.  As best I can tell, it acts like the Frame Valid control is level sensitive, not edge sensitive.  In order to get a valid image, I need to put a wait-loop for FrameValid to de-assert (I jumpered FV to an unused Flag pin), then configure the PPI and DMA.  If I don't do this, the image is mis-aligned and distorted.  With my alignment code enabled, I can capture every image (640x480 @15fps), and they are clean and proper.

 

Also, there are no PPI error flags set in either mode.

 

Anyone else have this issue?

 

void VideoSensorFrameCapturePacked ( BYTE * usPTR )
{
UINT tempVar, tempX, tempY;

// dgl wait for frame to go LO before triggering
*pFIO0_FLAG_S = LED1; // debug pin
while ((*pFIO2_FLAG_D & PF40) != 0) ;
*pFIO0_FLAG_C = LED1; // debug pin

*pDMA1_0_X_COUNT = (PIXEL_PER_LINE*2) / DMA_COUNT_DIV; // 2 samples per pixel (luma/chroma)
*pDMA1_0_Y_COUNT = LINES_PER_FRAME;     // lines per frame from the sensor
*pDMA1_0_X_MODIFY = X_MODIFY;     

*pDMA1_0_Y_MODIFY = Y_MODIFY;    
*pDMA1_0_START_ADDR = usPTR;     


*pDMA1_0_CONFIG =   DMA2D | WDSIZE_32 | WRITE;

 
*pPPI0_FRAME = LINES_PER_FRAME + 1; //The PPI is set to receive X lines per frame add one
*pPPI0_COUNT = PPICOUNT;  //The PPI is set to stop receiving after X number of samples for each liene

*pPPI0_CONTROL = PPICTRL_DLEN8 | PPICTRL_DMA32 | PPICTRL_PACK | PPICTRL_NON656 | PPICTRL_RX;

*pDMA1_0_CONFIG |= DMAEN | DI_EN; // | DMA enable
ssync();

*pPPI0_CONTROL |= PORT_EN; // | Start PPI
ssync();

}

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