I am developing a project for ADAU1761 . A active OSC =24.576MHz clock connect to MCLK pin. Now LINK and COMPILER , verify PLL status always keeps unlocking. checked the 24.576MHz clock by scope, the MCLK path just from clock generator to MCLK pin. used 12.288MHz clock , can be locked .
1761 DATASHEET donoes not say the input MCLK charecteriistic detail .