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MCLK to ADAU1761 cannot be locked in Sigmastudio

Question asked by bjash on Oct 12, 2013
Latest reply on Oct 13, 2013 by bjash

Hi All

I am developing a project for ADAU1761 .  A active OSC =24.576MHz clock  connect to MCLK pin. Now  LINK and COMPILER , verify PLL status  always keeps unlocking. checked the 24.576MHz clock by scope,  the MCLK path just from clock generator to  MCLK pin. used 12.288MHz clock , can be locked .

1761 DATASHEET donoes not say the input MCLK charecteriistic detail .

Meican.

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