Hello, wher in the block diagram attached does blue screen get injected?
It's part of the Standard Definition Processor Block
Yes but which sub-block within the sdp block?
It is it's own block that would go to the output formatter, it's not listed as that is a very generalized block diagram. Why?
Well something is not right in our chroma path. When we pump in PAL composite video, we can see the output Y behave ok (matches the static video image of a white box we are using)
But the Cr and Cb are shifting all around (not locked , ie., in sync, and stable with Y).
The same video pumped to our 7180 device shows Y and Cr/Cb are lined up nicely with each other and stable.
When I output blue screen on the 7181 just for kicks, the Y and Cr/Cb are lined up with each other. Just an observation that I thought might provide a clue or at least some useful info?
Probably not helpful to know where it is then.
If Cb/Cr aren't stable-- probably some chroma subcarrier-related issue. Maybe the part is not recognizing that it's PAL?
As I recall, someone at your company was working on SD RGB application. Is that correct?
Yes, Jeff Saarela and I. Disregard this blue screen question. I think we have found an issue with our FPGA that accepts adv7181 YCC
I’ll try to be more in sync with Jeff when it comes to submitting eng zone questions, try to steer toward just one of us doing the entries.
Yes, Jeff. I frequently see that people work at the same company but I'm never sure if they are working on a similar project. Good luck with this!
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