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BF527 PLL setting

Question asked by GregTyma on Oct 10, 2013
Latest reply on Oct 16, 2013 by JoeT

Could you explain me which way of PLL setting for BF527 is correct?

There is information:

"Note that the divisor ratio must be chosen to limit the system

clock frequency to its maximum of fSCLK. The SSEL value can be

dynamically changed without any PLL lock latencies by writing

the appropriate values to the PLL divisor register (PLL_DIV)

using the bfrom_SysControl() function in the on-chip ROM."

in document

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527: Blackfin Embedded Processor Data Sheet (Rev D, 07/2013) (pdf, 6193 kB)

 

 

But there is also anomaly: 05000440 - bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register.

So, is this anomaly still valid or not (for rev.0.2)?

 

 

Could you inform me also when frequency changing process starts?

When idle instruction is issued or write to any PLL (PLL_DIV, PLL_CTL, PLL_LOCKCNT) register triggers it? 

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