I have synced up with GITHUB and have the "lastest" version of the no-os drivers, but it does not compile. Is there a version i should be pointing to that matches up with the latest HW drop?
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Can you give us more details regarding you problems?
I suggest you to use these release:
- SW: https://github.com/analogdevicesinc/no-OS/releases/tag/fmcomms1_ver_1_09_13_2013
- HDL: https://github.com/analogdevicesinc/fpgahdl_xilinx/releases/tag/ad_fmcomms1_ver_1__2013_08_23
Thanks for the quick reply. The issue that I am having is that the DAC output looks saturated when looking on a spectrum analyzer and the ADC chipscope plots also appear to be saturated. And with the various code bases and trying to follow the different discussion posts, I am having a hard time figuring out if there is a problem with the board or is it just an error in which versions i am using, etc...I am trying the tags you suggested as we speak. Looks like the pcores are a bit different for FFT, so I am regenerating those cores.
I used the .bit and .bmm files without regenerating them along with sw.elf generated by SDK with the files from the tag you provided and the ADC tests do not work anymore. I changed the ML605 in main.c to KC705...and the DAC output appears to be saturated when probed on a spectrum analyzer...any thoughts?
These days I'm out of the office, so I can't test the projects. I will do that next week, when I will return. I will let you know my results.
I re-built the .bit file with the latest HDL code base and now the tests all pass. The DAC ouput/ADC input is still clipping, not sure if changing the RX gain would help at all. I put an attenuator in the path and I get decent looking sine waves. There does seem to be an I/Q imbalance which I am trying to fix...so, if you could let me know the best way to reduce the output power from the DAC (i.e. which register to scale the DDS, i thought i used the correct one but it seems to have no effect.) and also how to fix the I/Q imbalance...
Here you can find the PCORE Register Map: http://wiki.analog.com/resources/fpga/xilinx/hints/pcore_register_map
In the DAC CHANNEL section you can find details about the DDS configuration. To change the scale you have to write the REG_CHAN_CNTRL_1 register. You can find an example here: https://github.com/analogdevicesinc/no-OS/blob/master/ad9361/sw/dac_core.c#L181
To set the IQ correction you can use the XCOMM_SetDacIqCorrection() function:
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