I have the Ez_FPGA programmed using a Xilinx platform jtag cable. This has programmed the serial flash.
I allow the FPGA to be programmed from the serial flash by populating the following jumpers as specified by the manual:
JP1, M0, M1, M2.
I have the FPGA connected to the DSP using the expansion interface.
The FPGA is being powered by the DSP and the appropriate jumpers are set to do this.
The DSP will not communicate with VisualDSP (via HPUSB-ICE) unless I populate jumper JP3 on the FPGA.
As soon as I populate JP3, the FPGA dumps its currently running code and is no longer being programmed by the serial flash.
I have tried populating JP2, as it sounded like the appropriate one to use. However the DSP will only communicate to the PC when JP3 is set, again I lose functionality on the FPGA.
How can I have the FPGA run the code from the serial flash and still be able to control the BF537??
The configuration program jumper, JP3, connects the program bit of the FPGA to the Blackfin processor’s flag pin. By default, JP3 is populated. The jumper assures that the program bit is asserted by the Blackfin processor to initiate the FPGA programming through development software
The configuration done jumper, JP2, connects the done bit of the FPGA to the Blackfin processor’s PF3 flag pin of the ADSP-BF533 and
ADSP-BF561 EZ-KIT Lites or PF14 flag pin of the ADSP-BF537 EZ-KIT Lite. By default, the jumper is populated and acts as a monitor for the
done bit by the Blackfin processor (the bit indicates that the FPGA programming is complete).