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HDL Version 2 BUILD timing errors.....

Question asked by ROBFRO on Oct 8, 2013
Latest reply on Nov 11, 2013 by DragosB

I am trying to BUILD the latest no-os demonstration.

I downloaded this HDL Version 2 design.


I am getting timing errors.


INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in

   the unconstrained paths section(s) of the report.

INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model.  For the details of

   this model, and for more information on accounting for different loading conditions, please see the device datasheet.



Timing summary:



Timing errors: 7  Score: 965 (Setup/Max: 965, Hold: 0)


Constraints cover 8706053 paths, 2 nets, and 354517 connections


Design statistics:

   Minimum period:  11.613ns (Maximum frequency:  86.110MHz)

   Maximum path delay from/to any node:   5.364ns

   Maximum net skew:   2.977ns

   Maximum output delay after clock:   2.816ns



Analysis completed Tue Oct 08 11:53:01 2013



Generating Report ...


Number of warnings: 9

Number of info messages: 4

Total time: 3 mins 52 secs



xflow done!

touch __xps/system_routed

xilperl C:/xilinx/14.4/ISE_DS/EDK/data/fpga_impl/ -error yes implementation/system.par

Analyzing implementation/system.par


ERROR: 1 constraint not met.


PAR could not meet all timing constraints. A bitstream will not be generated.


To disable the PAR timing check:


1> Disable the "Treat timing closure failure as error" option from the Project Options dialog in XPS.




2> Type following at the XPS prompt:

XPS% xset enable_par_timing_error 0


make: *** [implementation/system.bit] Error 1




Any suggestions?