Am trying to move some working 533 code over to one core of 561
I build a two core 561 project -- with one of the core's running idle -- then added the code from the working project and got it to compile.
I was under the impression that the second core would not start until the code -- adi_core_b_enable -- was run from core A:
However VDSP seems to allow that core-B to run by itself -- which means that when I try to download both executables into their represtative cores -- VDSP says that it can't stop the other core, the system wants to disconnect and the crashing everything
DO I ned to find a way to set bit 5 of the SICA_SYCR via VDSP?
Message was edited by: Michael Smith