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Register setting for normal TDM mode in AD1934

Question asked by FalkB on Oct 7, 2013
Latest reply on Oct 8, 2013 by FalkB

Hello,

 

I try to use an AD1934 in TDM mode with 8 channels. My register setting is as follows.

 

ad1934_write_reg(0, 0b10011101);// PLL0: DAC active, PLL intput MCLK, MCLKO off, Input 512xfs, PLL power down
ad1934_write_reg(1, 0b00000011);// PLL1: reference on, clock source MCLK, DAC clock MCLK
ad1934_write_reg(2, 0b00100000);// DAC0: I2S mode, SDATA delay 16, 44,1kHz, normal operation
ad1934_write_reg(3, 0b00000100);// DAC1: BCLK normal, BCLK from DBCLK, BCLK slave,
// LRCLK slave, left low, 8 channels, latch midcycle
ad1934_write_reg(4, 0b00011000);// DAC2: DAC noninverted, 16 bit/word, flat De-emphasis, unmute

 

Doing so, I can only make sound comming out on OL1 and OR1. OL1 is according to the datasheet the first in the TDM frame and works OK. But OR2 seems to be located on channel position 4 instead of channel 1 as shown in figure 10 in the datasheet. All other channels seem not to work.

The AD1934 is clocked by 22,579200 MHz supplied by an XO on MCLKI, DBCLK is 11,289600 MHz, directly derived from the very same XO clock inside an FPGA. DLRCLK is 44,1kHz.

 

I can write and read back all configuration registers. All other register have their default value, which means, there is no mute or attenuation.

 

I tried using all four modes in DAC0,

 

Stereo(normal)

TDM (daisy chain)

DAC aux mode (DAC-, TDM-coupled) and

Dual-line TDM.

 

Only Stereo works, but only for two channels.

 

Here is a part of my schematic, if this helps.

 

 

Please advice.

 

Regards

Falk

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