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Video with ADV7511 on the VC707

Question asked by tomatobiscuit on Oct 4, 2013
Latest reply on Nov 27, 2017 by roy5220

Hi!

 

We're having trouble getting any video output with our current I2C configuration. We've implemented a simple test in Verilog that sends out a one color once the I2C is configured. We're using the reference values found in the ADV7511 Programming Guide for the 1080p format. Hopefully I've got it right translating the "Placement" to mean the front porch length found in VGA timing diagrams and "Delay" to mean "front porch + back porch + sync length". The register configurations is as follows:

 

/* CONFIGURATION REGISTERS */
   assign ADDR[ 0] = 8'h41;     /* 00 - power-up power-down */
   assign ADDR[ 1] = 8'h0B;     /* 01 - SPDIF config */
   assign ADDR[ 2] = 8'h14;     /* 02 - audio sample word length */
   assign ADDR[ 3] = 8'h15;     /* 03 - input video format */
   assign ADDR[ 4] = 8'h16;     /* 04 - color depth, video input edge, RGB */
   assign ADDR[ 5] = 8'h17;     /* 05 - vsync hsync polarity */
   assign ADDR[ 6] = 8'h3C;     /* 06 - VIC to send to Rx */
   assign ADDR[ 7] = 8'h0A;     /* 07 - audio type select */
   assign ADDR[ 8] = 8'h55;     /* 08 - video output format */
   assign ADDR[ 9] = 8'h73;     /* 09 - audio channel count */
   assign ADDR[10] = 8'h9D;     /* 10 - input pixel clock divide */
   assign ADDR[11] = 8'hAF;     /* 11 - HDCP encryption, HDMI mode */
   assign ADDR[12] = 8'hD7;     /* 12 - vsync hsync durations */
   assign ADDR[13] = 8'hD8;     /* 13 - */
   assign ADDR[14] = 8'hD9;     /* 14 - */
   assign ADDR[15] = 8'hDA;     /* 15 - */
   assign ADDR[16] = 8'hDB;     /* 16 - */
   assign ADDR[17] = 8'hF9;     /* 17 - fixed I2C address */


   /* REQUIRED REGISTERS (reserved) */
   assign ADDR[18] = 8'h3B;     /* 18 - */
   assign ADDR[19] = 8'h44;     /* 19 - */
   assign ADDR[20] = 8'h48;     /* 20 - */
   assign ADDR[21] = 8'h94;     /* 21 - */
   assign ADDR[22] = 8'h96;     /* 22 - */
   assign ADDR[23] = 8'h98;     /* 23 - */
   assign ADDR[24] = 8'h99;     /* 24 - */
   assign ADDR[25] = 8'h9A;     /* 25 - */
   assign ADDR[26] = 8'h9B;     /* 26 - */
   assign ADDR[27] = 8'h9C;     /* 27 - */
   assign ADDR[28] = 8'h9F;     /* 28 - */
   assign ADDR[29] = 8'hA1;     /* 29 - */
   assign ADDR[30] = 8'hA2;     /* 30 - */
   assign ADDR[31] = 8'hA3;     /* 31 - */
   assign ADDR[32] = 8'hA4;     /* 32 - */
   assign ADDR[33] = 8'hA5;     /* 33 - */
   assign ADDR[34] = 8'hA6;     /* 34 - */
   assign ADDR[35] = 8'hA7;     /* 35 - */
   assign ADDR[36] = 8'hA8;     /* 36 - */
   assign ADDR[37] = 8'hA9;     /* 37 - */
   assign ADDR[38] = 8'hAA;     /* 38 - */
   assign ADDR[39] = 8'hAB;     /* 39 - */
   assign ADDR[40] = 8'hB9;     /* 40 - */
   assign ADDR[41] = 8'hBA;     /* 41 - */
   assign ADDR[42] = 8'hBB;     /* 42 - */
   assign ADDR[43] = 8'hC7;     /* 43 - */
   assign ADDR[44] = 8'hCD;     /* 44 - */
   assign ADDR[45] = 8'hCE;     /* 45 - */
   assign ADDR[46] = 8'hCF;     /* 46 - */
   assign ADDR[47] = 8'hD0;     /* 47 - */
   assign ADDR[48] = 8'hD1;     /* 48 - */
   assign ADDR[49] = 8'hD2;     /* 49 - */
   assign ADDR[50] = 8'hD3;     /* 50 - */
   assign ADDR[51] = 8'hD4;     /* 51 - */
   assign ADDR[52] = 8'hD5;     /* 52 - */
   assign ADDR[53] = 8'hD6;     /* 53 - */
   assign ADDR[54] = 8'hDC;     /* 54 - */
   assign ADDR[55] = 8'hDD;     /* 55 - */
   assign ADDR[56] = 8'hDE;     /* 56 - */
   assign ADDR[57] = 8'hDF;     /* 57 - */
   assign ADDR[58] = 8'hE0;     /* 58 - */
   assign ADDR[59] = 8'hE2;     /* 59 - */
   assign ADDR[60] = 8'hE3;     /* 60 - */
   assign ADDR[61] = 8'hE4;     /* 61 - */
   assign ADDR[62] = 8'hFA;     /* 62 - */
   
   /* values that have to be written to above registers */
   reg [7:0]   DATA [0:62];
   
   /* CONFIGURATION REGISTERS */
   assign DATA[ 0] = 8'h10;     /* 00 - power on ADV7511 */
   assign DATA[ 1] = 8'hCE;     /* 01 - */
   assign DATA[ 2] = 8'h02;     /* 02 - 16-bit */
   assign DATA[ 3] = 8'h00;     /* 03 - 24-bit RGB 4:4:4 */
   assign DATA[ 4] = 8'h32;     /* 04 - color depth 8-bit, rising edge */
   assign DATA[ 5] = 8'h02;     /* 05 - high polarity */
   assign DATA[ 6] = 8'h02;     /* 06 - */
   assign DATA[ 7] = 8'h10;     /* 07 - SPDIF, MCLK */
   assign DATA[ 8] = 8'h00;     /* 08 - RGB output */
   assign DATA[ 9] = 8'h01;     /* 09 - 2-channel audio */
   assign DATA[10] = 8'h60;     /* 10 - clock not divided */
   assign DATA[11] = 8'h06;     /* 11 - disable encryption, HDMI */
   assign DATA[12] = 8'h16;     /* 12 - hsync front porch = 1080p */
   assign DATA[13] = 8'h02;     /* 13 - hsync duration    = 1080p */
   assign DATA[14] = 8'hC0;     /* 14 - vsync front porch = 1080p */
   assign DATA[15] = 8'h10;     /* 15 - vsync duration    = 1080p */
   assign DATA[16] = 8'h05;     /* 16 - */
   assign DATA[17] = 8'h00;     /* 17 - set to non-conflicting address */
   
   /* REQUIRED REGISTERS (reserved) */
   assign DATA[18] = 8'hE0;     /* 18 - */
   assign DATA[19] = 8'h00;     /* 19 - */
   assign DATA[20] = 8'h00;     /* 20 - */
   assign DATA[21] = 8'hC0;     /* 21 - */
   assign DATA[22] = 8'h00;     /* 22 - */
   assign DATA[23] = 8'h03;     /* 23 - */
   assign DATA[24] = 8'h02;     /* 24 - */
   assign DATA[25] = 8'hE0;     /* 25 - */
   assign DATA[26] = 8'h18;     /* 26 - */
   assign DATA[27] = 8'h30;     /* 27 - */
   assign DATA[28] = 8'h00;     /* 28 - */
   assign DATA[29] = 8'h00;     /* 29 - */
   assign DATA[30] = 8'hA4;     /* 30 - */
   assign DATA[31] = 8'hA4;     /* 31 - */
   assign DATA[32] = 8'h08;     /* 32 - */
   assign DATA[33] = 8'h04;     /* 33 - */
   assign DATA[34] = 8'h00;     /* 34 - */
   assign DATA[35] = 8'h00;     /* 35 - */
   assign DATA[36] = 8'h00;     /* 36 - */
   assign DATA[37] = 8'h00;     /* 37 - */
   assign DATA[38] = 8'h00;     /* 38 - */
   assign DATA[39] = 8'h40;     /* 39 - */
   assign DATA[40] = 8'h00;     /* 40 - */
   assign DATA[41] = 8'h00;     /* 41 - */
   assign DATA[42] = 8'h00;     /* 42 - */
   assign DATA[43] = 8'h00;     /* 43 - */
   assign DATA[44] = 8'h00;     /* 44 - */
   assign DATA[45] = 8'h01;     /* 45 - */
   assign DATA[46] = 8'h04;     /* 46 - */
   assign DATA[47] = 8'h3C;     /* 47 - */
   assign DATA[48] = 8'hFF;     /* 48 - */
   assign DATA[49] = 8'h80;     /* 49 - */
   assign DATA[50] = 8'h80;     /* 50 - */
   assign DATA[51] = 8'h80;     /* 51 - */
   assign DATA[52] = 8'h00;     /* 52 - */
   assign DATA[53] = 8'h00;     /* 53 - */
   assign DATA[54] = 8'h00;     /* 54 - */
   assign DATA[55] = 8'h00;     /* 55 - */
   assign DATA[56] = 8'h10;     /* 56 - */
   assign DATA[57] = 8'h01;     /* 57 - */
   assign DATA[58] = 8'h3C;     /* 58 - */
   assign DATA[59] = 8'h00;     /* 59 - */
   assign DATA[60] = 8'h00;     /* 60 - */
   assign DATA[61] = 8'h60;     /* 61 - */
   assign DATA[62] = 8'h00;     /* 62 - */

 

Is there anything we're missing? We're generating all the syncs and data enables from our Verilog module.

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