I am planing to build an all digital PLL using a DDS as VCO replacement. As far as I am informed, all PLL ICs from ADI have an internal phase/frequency detector to compute the error signal. However, they all come with a sequential charge pump. In my setup, a central processing unit (or FPGA) is supposed to implement the regulation (PID) unit. In my opinion, it would be advantageous to process the error signal digitally. A charge pump would generate an analog signal which I try to circumvent. On the website I found the AD9901, which is just a single phase/frequency detector without any other parts. It looks like this IC is precisely what I am looking for. My question is, if this is the newest revision, because I did not find any other ICs concerning this issue, or if there is an alternative approach. And further, how I can properly convert my two analog RF signals (which are to be compared with the AD9901, about 160MHz) into TTL level. I know that a fast reel to reel comparator is usually used in this case, but maybe there are some more hints I should take into account. Thank you.