If Hsync width is short, PLL is not locked when we input analog RGB signal to ADV7842,
(XTAL 28.63636MHz、Pulse width about 80ns)
We can select the number of clock about DEGLITCH_FILTER using CPmap 0xF5 DIG_SYNC_DEGLITCH_REDUCE
But it is 2 type only (2clock or 5clock)
When we select 2clock, PLL is not locked because the pulse of 80ns is removed.
We find the method to avoid same issue at EZ.
We tested this issue with changing pulse width.
Then test result says that the threshold value which pulse is removed is (the number of clock+1) /28.63636MHz.
We think below.
This issue will be closed if we can select the number of clock under 1 clock or filter can be bypassed.
So please let me know your advice about below question
1. Can we disable DEGLITCH_FILTER of ADV7842 using same method ?
2. Can we select any number of clock except 2 or 5clock setting ?
For example, we can select 0 to 7 clock and etc….
3. If possible, please let me know its method.
If we can not select above settings and there is any method to avoid this issue,
please let me know your advice.