I would like to know how to properly configure SPI Mode 0 (CLKPHA=0, CLKPOL=0), using CCES (not VisualDSP++) together with the System Services and Device Drivers API v2.0?
My hardware platform is the BF592 EZ Kit Lite (with JTAG debugging via the USB ICE 100B) .
I have got the example code, SPI_flash_read, running on the board. This involves the DSP sending 0x9f out over the SPI and receiving 0x20, 0x20, 0x15 from the flash. The example code uses SPI Mode 3 (CLKPHA=1, CLKPOL=1).
I've configured the UART interface to output debug information to a terminal on my PC - which I use to monitor the SPI Tx and Rx buffers (in the ADI_SPI_TRANSCEIVER structure). I also have an oscilloscope which I monitor the SPI signals, via the corresponding pins on the P4 connector.
According to the documentation for the onboard flash (M25P16), it should be able to support both SPI Modes 0 and 3.
The first issue I encountered when trying to use SPI Mode 0, was how to go about setting CLKPHA on the BF592. There is an element of confusion about this in the SSDD v2.0 API Reference section for the BF592:-
beneath the entry for adi_spi_SetClockPolarity() there is a note to also see adi_spi_SetClockPhase(). However there is no such function listed for the BF592. It only seems to be listed under the section for ADSP-BF60x SPI Device Driver. Thought I'd try using the function anyway, just in case the documentation was out of date - I tried to call the adi_spi_SetClockPhase() function in my code, but it wasn't recognised (couldn't be resolved).
I was able to flip between SPI Modes 0 and 3 via doing the following:-
SPI Mode 0:
call adi_spi_SetHwSlaveSelect() with true for the bHWSlaveSel variable, together with
calling adi_spi_SetClockPolarity() with true for the bActiveHigh variable.
For SPI Mode 3, the settings are
call adi_spi_SetHwSlaveSelect() with false for the bHWSlaveSel variable, together with
calling adi_spi_SetClockPolarity() with false for the bActiveHigh variable.
I verified these settings in the SPI_CTL register using the JTAG debugger.
When I changed the example code to use SPI Mode 0, I no longer got the expected data back from the flash chip (0x20, 0x20, 0x15).
However, if I went in and hacked the code and forced the SPI select line low before the SPI transfer, then it worked - in SPI Mode 0 I was able to get the right data back from the flash.
The hack I used to set the line low was as follows:-
*pPORTF_FER &= 0xfeff;
*pPORTFIO_DIR |= 0x100;
*pPORTFIO_CLEAR = 0x100;
The above hack doesn't seem very consistent with the SSDD v2.0 API approach, and I'm assuming there is a better (proper) way to configure things using SSDD v2.0?
Referring to the Hardware Reference doc for the BF592, there is a note about CPHA=0 operation, which seems to suggest that writing to the appropriate FLS bit in the SPI_FLG register is required. Is this the correct way to implement SPI Mode 0 in SSDD v2.0? A write to this register still doesn't seem completely consistent with how the rest of the SPI driver functionality is configured via the various SSDD v2.0 API functions.