I want to use a AD9959 DDS core to generate 4 RF signals up to 250MHz. The DDS will be provided by a 500MHz external clock; the PLL will be disabled. Since I want to reach fast switching between different phase tuning words I was planing to use the 4-bit serial mode (SDIO 0, 1, 2 and 3) at maximum SCLK 200MHz. As far as I understood, the SCLK has to be provided by the master unit (FPGA), which is sending the data. I was wondering, if the SCLK is connected to the REF_CLK (which is the same as SYS_CLK in this case) or needs to be in phase with REF_CLK? This would mean, to synchronize the DDS and FPGA. Otherwise, the FPGA could be "free running" and the merging of the new data sets take place on an IO_UPDATE.