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Serial Output Control register settings (2078) adua1701

Question asked by Bazeman on Oct 2, 2013

Hi all,

 

I need some help understanding the settings possible for the serial output control register setup of the adua1701 in combination with an external adc/dac.

 

The design is based on a 48kHz sample rate with a 12.288Mhz clock (the MCLKI is chosen as 256xfs). The ADC is set as master with Oversampling Ratio of 128fs (single rate) and the System Clock rate is 256fs.

 

I like to know the following:

1) The ADC is set to master so I assume I need to set the ADUA1701 (2078) M/S register to slave?

2) When the ADC is master, No setting is needed for the (2078) OBF and OLF register, right? 

 

But if adua1701 is Master and ADC slave, how do I set these registers correctly for the given system clock and sample rate? OBF setting can be: Internal clock/16 by /8 by /4 or by /2 and OLF setting can be: Internal clock/1024 by /512 or /256

 

3) What/Why I have to choose/define, or what is the best setting in this case, for the (2078) MSB register? Settings are: Delay by 1 / by 0 / by 8 / by 12 / by 16...

 

4) What/Why I have to choose/define, or what is the best setting in this case, for the (2078) OWL register? Settings are: 24Bits / 20Bits / 16Bits

 

Thanks in advance

 

Bazeman

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