RonSimpson

Re: AD7626 Interface Question

Discussion created by RonSimpson on Oct 1, 2013
Latest reply on Oct 2, 2013 by RonSimpson
Branched from an earlier discussion

Questions on AD7626 to FPGA interface:

 

The engineer before me (who really never got it to work) saw that the AD7626 needs to be sent a convert pulse every 9uS to keep it 'alive'.  He needs data every 90uS so he only clocked out the data 1/10 of the time.  To say it another way; most of the convert pulses do not have 16 clocks.  The one time where the data is clocked out the data seems not to be valid. 

 

By experiments; it looks like every convert pulse must have the data clocked out to keep the part 'alive'.    Can some one confirm that sending only the convert pulse (with out clocking out the data) will not keep the part working.

 

My experiment: Sent a convert pulse every 9uS.

For pulse 1 through 9 (do not sent data clocks)  [the part appears to indicate that data is not available]

For pulse 10 (send 16 data clocks) [the part appears to indicate that data is not available]

For pulse 11 through 19 (send 16 data clocks) [data looks good]

For pulse 20 through 100 (do not sent data clocks)  [the part appears to indicate that data is not available]

Outcomes