Understanding of the following is correct about ADF4351?

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Value of PFD frequency is calculated by the following equation.

fpfd = REFIN × [(1+D)/(R×(1+T)] (Data sheet Page.11)

So, Value of 125kHz(DB23 bit of R3 is 0) is calculated by the following equation.

fpfd = 250MHz × [1/(1023×(1+1))]

This value is used as the clock for the band select logic.

When using a value greater than 125kHz in Low PFD mode,

there is a possibility that the band select logic to malfunction.

When the required PFD frequency is higher than 125kHz, the divide ratio

should be set to allow enough time for correct band selection.

When the PFD frequency is greater tha 125 kHz, you need to use the Band Select Clock Divider value in R4 DB[19:12] to divide down to a frequency below 125 kHz.

Normally your PFD frequency will be much greater than 125 kHz. The typical PFD frequency range is from 10 MHz - 32 MHz. The lower your PFD frequency, the worst your phase noise.

Frac-N PLLs are not like Int-N PLLs. In Int-N PLLs, the channel spacing equals the PFD frequency. In Frac-N PLLs, the channel spacing equals the PFD frequency divided by MOD. In the ADF4351, MOD can be up to 4095.