I am trying to use the ADAU1961 as simple stereo ADC with external MCLK (12.288MHz) with 256×Fs and 48kHz sample rate.
If I set up the device to generate the BCLK and LRCLK (master mode operation), the clocks are correct but the data coming out changes
on both edges of the BCLK.
If I enable only one channel, I see data (changing on both edges of BLCK) during both level of LRCLK. (see the attached picture)
If I change the bus mode to slave, every other settings not affected, and I feed the BLCK and MCLK to the ADAU1961, the data is correct,
changing only on falling edge and the audio sounds good.
R0 (0x4000) : 0x01
R15 (0x4015) : 0x01
R16 (0x4016) : 0x00
R17 (0x4017) : 0x00
R18 (0x4018) : 0x00
R19 (0x4019) : 0x31 (one ADC channel is enabled)
Thanks for your help.