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ADV7619 input TMDS clock modulation

Question asked by mike_ackee on Oct 1, 2013
Latest reply on Nov 27, 2013 by GuenterL

I am having a problem with the ADV7619 when receiving video with low frequency clock modulation. This is being generated by a third party piece of equipment and I am told that it complies with spread-spectrum clocking norms.

 

The symptoms I see are that the Data Enable from the ADV7619 mostly works, but very often the first active line of video is missing with no data enable asserted. Also, there are occasional glitches on Vsync and hsync.

 

Whilst I do not (yet) have a spec for the clock modulation, I can monitor the clock frequency using the TMDSFREQ registers. It seems to be varying between 185.5390625 MHz and 185.703125MHz. The input is 1080p50 at 10-bits per colour, so I would expect the clock to centre at 185.625MHz, equivalent to a pixel clock of 148.5MHz.

 

The TMDS_PLL_LOCKED register indicates a locked status, but the DCFIFO_LEVEL is varying all over the place and does indicate that it cannot lock. This leads me to believe that the problem is that the DPLL is unable to lock to the fluctuating clock frequency.

 

As the DPLL block is a black box as far as all specs and apps notes are concerned, please can you advise on what I can do to get the system working.

 

Thank you.

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