AnsweredAssumed Answered

DRAM fetches causes pipeline stalls in BF516

Question asked by AviMagos on Oct 1, 2013
Latest reply on Oct 4, 2013 by CraigG



I'm using BF516F processor, with the visual DSP 5.0.10 (update 10) environment.


The Programming reference, page 6-68 ("interlocked Pipeline" sub-chapter) states that when executing a load instruction, only the "loaded" register is marked as busy. Hence I can fetch data from external memory, and in the mean-time execute other instructions, not involving the loaded register, without causing stalls and bubbles in the pipeline.

However In practice I don't see that it really happens:


I have written the following code:

     R0 = DRAM fetches causes pipeline stalls in BF516;      //fetch data from DRAM

     R1 = 0;

     R2 = 0;

     R3 = 0;

     R4 = 0;

     R5 = 0;


When I ran simulation and looked in the pipeline viewer, as soon as the load instruction reached "execute1" a stall occurs for 6 cycles!


Why is that? Is it only because the simulator is not "smart" enough? Can you verify that in practice when the code run on the processor itself the stalls do not occur?





Message was edited by: Aviel Kisliansky
 Sorry - some kind of html code jumbled the example I gave - the first line is of course R0 = { I1 }  (square brackets [ instead of { of course...)


Message was edited by: Aviel Kisliansky
 Hi Craig - There is some bug in the EZ that doesn't allow me to reply - so I simply edit this message....
 You've asked me to me open a separate private support request - I've done so and still no reply for over 1 week.