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CN0290: Extending the Low Frequency Range of a High Performance Phase Locked Loop
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on Sep 30, 2013
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AD9371 JESD204B interface - board design validation
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I am using the AD7476 1 MSPS serial ADC. The fclk frequency is 12 MHz. I see 4 short 20 ns pulses on the SDATA line from the ADC framed by the chip select line, /CS. The short SDATA pulses are always 4 clock pulses apart, 320 ns. If anyone can explain