I have a question about rise time / fall time of CLK of ADV7511W.Could you tell me requirement rise time / fall time (Tr/Tf) spec for CLK and SCLK?
The I2C interface is designed to work with I2C standards up to 400kHz. The inductry standards specify the bus capacitance and pull up resistors which define the bus rise/fall times. So no, there is no 7511 defined I2C rise/fall times, just that it meets the industry standards.
Thank you for your reply.
About SCLK, I mentioned SCLK pin (pin No.9).It's not I2C CLK. It's I2S Audio Clock Input.Also, how about CLK pin (pin No. 53 Video Input Clock)?Could you tell me requirement rise time / fall time (Tr/Tf) spec for CLK(pin No. 53) and SCLK(pin No.9)?
Sorry about misunderstanding the question. We don't have have hard rise/fall times for the digital outputs. You will need to utilize the IBIS files found at http://ez.analog.com/docs/DOC-1740
with signal integrity tools to determine the timing in your system. True measurements are dependent on test system setup .
The CLK(pin No. 53) and SCLK(pin No.9) are input pins.Don't you have the required rise/fall times spec for the inputs?
Let me ask see if I can find an answer to input rise/fall timing
Thank you for your help for this question.Can you get the answer input rise/fall timing spec?
No answers yet, pinging the sources again.
We don't have any Tr/Tf specifications for these signals. I suggest using good design practice of the rise/fall time < 10% of the clock period. What is important is that the data line setup and hold parameter are meet before the clock line goes through the mid point
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