We have an application that I think the AD9434 would be ideal for if I'm interpreting the data sheet correctly. We need to have a 500MSPS ADC in an application where the ADC sits in a very low power mode, but a "trigger event" wakes up the ADC in a very short amount of time (<100nS, preferably <25nS), runs for a short amount of time at 500MSPS, and then goes back to sleep. The "Power Dissipation and Power-Down Mode" section, in the last paragraph, describes the "standby state" when the clock <50MHz, but "Upon reactivating the clock, the AD9434 resumes normal operation after allowing for the pipeline latency." It's not clear how to interpret this statement in light of Figure 31. It would have been helpful to take those curves out to the left a little to show the ADC going into the "standby state," and / or it's not clear how the "Modes" bits in the ADC function registers affect this mode. Bottom line, this part might be ideal IF we could run it at 40mW in the "standby state," and then wake it up in <100nS (again preferably <25nS), simply by changing the clock from <1MHz to 500MHz in our FPGA based upon our trigger.Figures 2 & 3 imply to me the "pipeline latency" is 15 clocks. Is that correct?