AnsweredAssumed Answered

ADV7393 Input Supports and Configuration.

Question asked by Babu on Sep 25, 2013
Latest reply on Oct 2, 2013 by FrankK

Hi...

 

     I am using the ADV7393 Video Encoder Chip in myproject.

 

In which my requirement is to send SD PAL RGB(4:4:4)  16Bit (Blue-5 Green- 6 Red- 5 lines data format) 625 line progressive input and CVBS output. For this, as per data sheet(REV. E) guidelines, the TABLE 94 is used for Configuring the Chip, and 27Mhz Clock is connected to the CLK_IN pin.

 

     But I have the Doubts if it supports the Progressive input are what?  Because, As mentioned in data sheet(Rev. E) page no 92 the SD configuration Scripts supports the (625i - PAL) Interlaced inputs only, but in that same data sheet page no 52 mentioned as its supports the SD progressive method also, by setting the Address(0x88) bit 1 set as "1".

 

     If it supports the progressive inputs means, Kindly tell me..

          1. Which configuration Table want to follow?

          2. Input Clock What ?

          3. Hsync and Vsync timing what?

          4. Blanking timings in Hsync and Vsync ?

 

     Else it supports only the interlaced inputs means, for that also tell me,         

          1. Which configuration Table want to follow?

          2. Input Clock What ?

          3. Hsync and Vsync timing what?

          4. Blanking timings in Hsync and Vsync ?

         

 

Outcomes