I can't figure how the chained DMA works when program-controlled interrupts bit is set.
I receive blocks of data from SPORT. Each block has a length of 2048 words. Data is transmitted by both channels (A and B). Also I need to implement buffering of this data. Buffer should be able to store 5 blocks of data. For this purpose I use chained DMA. So I configure the TCBs like this:
#define DMA_OFFSET 0x80000
.VAR tcb_sport1a_adc_buffer1 = (tcb_sport1a_adc_buffer2 + 3 - DMA_OFFSET) | BIT_19, 2048, 1, sport1a_adc_buffer1 - DMA_OFFSET);
.VAR tcb_sport1b_adc_buffer1 = (tcb_sport1b_adc_buffer2 + 3 - DMA_OFFSET) | BIT_19, 2048, 1, sport1b_adc_buffer1 - DMA_OFFSET);
.VAR tcb_sport1a_adc_buffer2 = (tcb_sport1a_adc_buffer3 + 3 - DMA_OFFSET) | BIT_19, 2048, 1, sport1a_adc_buffer2 - DMA_OFFSET;
.VAR tcb_sport1b_adc_buffer2 = (tcb_sport1b_adc_buffer3 + 3 - DMA_OFFSET) | BIT_19, 2048, 1, sport1b_adc_buffer2 - DMA_OFFSET;
and so on till tcb_sport1a_adc_buffer5, which points again to tcb_sport1a_adc_buffer1.
.VAR tcb_sport1a_adc_buffer5 = (tcb_sport1a_adc_buffer1 + 3 - DMA_OFFSET) | BIT_19, 2048, 1, sport1a_adc_buffer5 - DMA_OFFSET);
.VAR tcb_sport1b_adc_buffer5 = (tcb_sport1b_adc_buffer1 + 3 - DMA_OFFSET) | BIT_19, 2048, 1, sport1b_adc_buffer5 - DMA_OFFSET);
As far as I understand now I have a circular buffer with a capacity of 5 blocks of data 2048 words each (if to count for both channels - 4096 words each). BIT_19 (PCI) of CP register is set so I expect to have an interrupt after every received block.
The point is that when I run the program DMA interrupt occurs only after receiving 5 blocks. I can see it by setting a breakpoint and looking at the memory. All buffers (sport1a_adc_buffer1 - sport1a_adc_buffer5) contain data after the first interrupt!
If I don't set BIT_19 I don't receive interrupt at all. This is clear. But I don't understand why I don't get DMA interrupt after each received block if BIT_19 is set. Could you please clarify the situation. Thanks.