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Abort counter enable feature of SMC.

Question asked by Nabeel Employee on Sep 23, 2013
Latest reply on Dec 16, 2014 by Praveen_H

When ARDY is enabled for extended Asynchronous SRAM read bus cycle, to avoid stalls in case of erroneous ARDY behavior, the ARDYABRTEN bit can be set to enable the ARDY Abort Counter. If ARDY abort counter is enabled, then the counter starts counting down as soon as the programmed read/write access cycles expire, this is a fixed 6 bit wide counter and counts a fixed 64 cycles after which if ARDY is still not asserted, it aborts the access and returns an error response back on the AXI system bus. This ensures that processor/test does not hang in case ARDY is not sampled correctly.