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Gating Core clock on CM40x

Question asked by Nabeel Employee on Sep 23, 2013

Dynamic power management(DPM) module on CM40x provides the option to gate the core clock. So using the DPM clock to the ARM core can be gated. But there is problem in gating the core clock on single core processor, because once the core clock is gated by core to itself there no way or un-gating it back directly to resume the normal operation.

 

The infrastructure available on CM40x helps in achieving this by using the DMA along with the TRU subsystem. The scheme is as follows:

 

  • Set up the TRU to map the trigger from Pin interrupt to one of the DMA channel
    • This will start the DMA once the external pin interrupt occurs
  • Set up the DMA to write to the DPM registers to un-gate the Core clock
    • Following code snippet maps the trigger from  PINT4 to MDMA:

*pREG_TRU0_GCTL = BITM_TRU_GCTL_EN;*pREG_TRU0_SSR42 = (TRGM_PINT4_BLOCK << BITP_TRU_SSR_SSR);                 

  • Gate the core clock by writing to DPM_CCBF_DIS register
  • Put the core in IDLE to initiate the Core clock gating
  • Wait for the external event to trigger the DMA which then writes to DPM_CCBF_EN register to un-gate the core clock.

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