We have a design using a 1GHz common clock to drive multiple AD9910s’ REF_CLK. The same 1GHz clock also goes to a clock divider chip (TI’s LMK04033) to generate phase aligned 250MHz, 125MHz and 62.5MHz. To synchronize multiple AD9910s, does AD9910 SYNC_IN have to come from a master AD9910 SYNC_OUT as showing on AD9910’s datasheet Figure 53? Can we use the 62.5MHz clock from the clock divider as SYNC_IN of all AD9910s?
Multiple FPGAs (using 125MHz as the main clock) in the same design also need to synchronize with all AD9910s. Can we clock the FPGA directly from the clock divider’s 125Hz, or should derive the 125MHz from AD9910’s PDCLK, SYNC_CLK or SYNC_OUT? Are the phase of AD9910’s PDCLK, SYNC_CLK and SYNC_OUT always aligned (or predictable) after each power on cycle?