I have observed in some forums where it is told that the capture range of CP based PLL is equal to the lock range.
Why is it like that?
What do you mean by 'capture range' and 'lock range'?
Tracking Range: This is the range of input data rates over which the PLL will
remain in lock.
Capture Range: This is the range of input data rates over which the PLL can
Source: AD800/AD802 datasheet
Please post this question in the Clock and Timing community: http://ez.analog.com/community/clock_and_timing
Simply put, the range over which the frequency of a Charge Pump based PLL is under control is limited by the range over which the charge pump can tune the PLL. If the frequency is within that range, then the PLL can settle (or lock) to that steady state.In order to attain lock in the first place, the frequency has to be within that same range so that the charge pump can intentionally affect change of the frequency and get it to settle into lock.
But while programming, we dont ensure anything.
We simply program the PLL counters. The VCO maybe at some frequency (depending upon it's state during switch OFF and the time b/w power on and off)
So can we ensure this: "In order to attain lock in the first place, the frequency has to be within that same range so that the charge pump can intentionally affect change of the frequency and get it to settle into lock."
It sounds like you are asking how to keep a part from getting into a runaway situation, and I suspect there are a variety of ways that this is addressed. Is there a specific part you are working with?
I'm using ADF4002 PLL IC and in the feedback path I'm using a mixer and DDS. The PLL is not able to track the fast tuning speed of DDS.
I need to widen the loop BW to enable it to track the DDS.
I believe that the capture range of PLL has some influence here. Although I'm tuning within the lock range of the PLL.
If the RFin is changing very quickly, it make sense that widening the loop bandwidth is required for the ADF4002 output to keep up with the DDS input. This is similar to settling time measurements in the Time Domain feature of ADIsimPLL - widening the loop bandwidth results in shorter settling times.
In a translation loop synthesizer, the DDS provides the frequency resolution BUT the PLL's loop filter still determines the settling time of the loop and thus the overall switching speed.
Yes it is right that the settling time of the translation loop is dependent on the loop BW of the PLL. But here I'm struggling with a peculiar problem. There is is a particular loop BW settling below which the loop becomes unstable (That means the VCO will go out of lock and saturate to either the upper end freq or lower end.
I need not increase the loop BW by a considerable amount,since I don't want the DDS spurs to go in through the loop filter.
I think this instability is caused due to the fast settling time of DDS.
Think about this for a moment -- any change in the DDS's output frequency is not responsible for the loop's being unstable. Changing frequency by reprogramming the DDS is analogous to changing frequency by programming the N divider. The design of the loop filter is a function of the PFD frequency and the VCO, so you should be able to design a stable loop filter with adequate phase margin using ADISIMPLL.
The N and R inputs of the PLL are not a linear system -- each is essentially a limiting amplifier followed by digital dividers that respond to logic levels. You actually get a reduction in the spurs from the DDS because of this and you don't have to design the loop filter at some very narrow bandwidth (causing instability) to suppress these. This is not the same case as in a fractional N PLL, where the N path integer dividers are constantly changing so their average value gives the proper fractional value of N and a narrower loop filter does help reduce the fractional spurs at the expense of settling time.
Thanks for the reply.
Is there any phenomenon such as "capture range" for ADF4002 or any other PLL in that family?
It would help to look at the circuit and look at loop bandwidth, and the PFD frequency of the ADF4002( should use the highest allowable in this configuraiton). It sounds like your circuit is a translation loop synthesizer. The settling time speed will be limited by the loop filter....regards,
Retrieving data ...