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AD7689 Front-end MUX / Gate drive voltages

Question asked by RandyGBO Employee on Sep 19, 2013
Latest reply on Sep 19, 2013 by maithil

I am assuming the front-end mux built into the AD7689 is using N & P channel FETs to switch in one of eight signal paths to the internal ADC. At extreme cold (<-40C... I know... it's not guranteed!) the muxes are starting to become sticky with the external channels being shorted to one another. I see that the issue has a signal level dependency which I can do nothing about but I'm also trying to discern whether this issue tracks the power supply voltage supplying the AD7689. Which supply, VDD or VIO, is used to power the drivers (internal to AD7689) driving the FET gates at the multiplexer? Are these control signals to the FET gates level shifted up to VDD levels internally? If not then I might can minimize the issue by tightening the requirements on my VIO power supply regulation (assuming that is where these signal are powered from). My VDD suply is already tightly controlled.


The device is configured as:      0xF1E4

//  B13 - Initial download; B12:9 - Unipolar Gnd Ref; B9:7 - CH0 1st, CH1 2nd;

//  B6 - Full Bandwidth; B5:3 - Ext Ref, Int Buff Disabled; B2:1 - disable Sequencer;

//  B0 - don't read back config; all bits shifted left 2 bits (<< 2)