In my application, I measure the decay of a weak (repetitive) magnetic field. To lower the noise, I measure the signal many times, and after digitizing, I stack the data. My current construction is based on an AD7621, but I want to increase revolution and speed.
In a new construction, I have considered the use of an AD7760 24bit SD converter or an AD7960 18bit SAR
Using an 18 bit converter with higher datarate gives me the possibility to design signal matched filters in an FPGA
My question is: How far can I continue to stack the data, and still reduce the noise with the squareroot of the number of samples?
Will "something" in the ADC show up?
I can not find any application notes on it.