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ADAU1446 CRC/WD + SigmaStudio

Question asked by Bat on May 23, 2010
Latest reply on Aug 3, 2010 by BrettG

So, here again. I have multiple questions :

 

1)I'm lost in SigmaStdio Version. On download page there is :

File downloaded are named :

SigmaStudio3110.zip (3.1.10 ?)

SigmaStudio3111beta.zip (3.1.11?)

In menu help "about" of sigmastudio, theses 2 versions are named :

3.1.20.375

 

One or the other of version don't change anything for me

 

2)

I'm trying to use Watchdog. Documentation state that :

57872 E210 Watchdog enable 1-bit enable register for watchdog timer 0
57873 E211 Watchdog Value 1 16 MSBs of the watchdog maximum count value 0
57874 E212 Watchdog Value 2 16 LSBs of the watchdog maximum count value 0

 

WD1 value seem to be 16bits (I wrote 0x1234, I read 0x1234)

but WD2 value seem to be only 8 bits - or only 8 bits wired - (I wrote 0x5678, I read 0x0078)

It's stated that it's the LSB word, so there is a byte missing ?

Or is it :

WD1 : ABCD

WD2 : xxEF

and value is ABCDEF ?

Other sigmaDSP seem to have 24 bits WD ...

 

Also, I don't understand exact meaning of :

"A program counter watchdog is used when the core performs block processing (which can span several samples)."

So how can I calculate (or estimate) maximum value ?

My first understanding was that it increase at each program step, and is raz at each frame. But it seem not that ?

 

My goal is to add a overall protection. I have remarked that in rude EMI condition, DSP seem to be "lost". In fact audio is not working anymore (output some time, every few seconds, audio sample not correct), but I can always access register. I treat EMI problem to not stop them from reaching processor, but I want to add the WD protection (if applicable for my finding) to add an auto restart feature.

 

In SigmaStudio, WD1 and WD2 value are not editable.(bug or not ? should it compute them himself ?)

 

3)

I'm using external µC to initialise ADAU1446, and I use exported files from sigmastudio.

These file have register data initial value like this :

/* Register Default - IC 1.DSP Regs */
#define R12_DSP_REGS_SIZE 84
ADI_REG_TYPE R12_DSP_REGS_Default[R12_DSP_REGS_SIZE] = {
0X00, 0X00, 0X00, 0X00, 0X00, 0X01, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X01, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X1F, 0X00, 0X00, 0X1C, 0X00, 0X05, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00, 0X00
};

 

Good. But in theses registers (here ones that are written to CRC1_IDEAL_VALUE)

CRC ideal value is not filled, WD value is not filled (I don't know if this one should be)

 

4)

For CRC use, I should program CRC ideal value. Where should I found it ? I have not find any trace of it, in any of the SigmaStudio env.

If it's not available, how can I calcul it ? Is it a simple CRC32 of each program word ?

Additionnaly, I don't succeed to have any CRC error.

I preset CRC1 et CRC2 value with random value. So it should be false (or I have a lot of luck). But I never see CRC error sticky of register 0xE205 going high ... If I enabled an MP with CRC error flag, it's the same, there is no CRC flag.

 

5)

Another bug in sigmastudio. Is use Level Detector/Multiple Bands/Pass Thru/Level Detector Designer. I have 14 bands

When I exported uC file for these project, header file are incorrect because there is no difference in constants between each band :

/* Module VuFreq - Level Detector Designer*/

#define MOD_VUFREQ_COUNT                               72

#define MOD_VUFREQ_DEVICE                              "IC1"

#define MOD_VUFREQ_ALG0_LEVDETGROW2001TCO_ADDR         41

#define MOD_VUFREQ_ALG0_LEVDETGROW2001TCO_FIXPT        0x00009D91

#define MOD_VUFREQ_ALG0_LEVDETGROW2001TCO_VALUE        SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0.00480857655249379)

#define MOD_VUFREQ_ALG0_LEVDETGROW2001TCO_TYPE         SIGMASTUDIOTYPE_FIXPOINT

#define MOD_VUFREQ_ALG0_LEVDETGROW2001DECAY_ADDR       42

#define MOD_VUFREQ_ALG0_LEVDETGROW2001DECAY_FIXPT      0x0000071C

#define MOD_VUFREQ_ALG0_LEVDETGROW2001DECAY_VALUE      SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0.000217013888888889)

#define MOD_VUFREQ_ALG0_LEVDETGROW2001DECAY_TYPE       SIGMASTUDIOTYPE_FIXPOINT

==> Here Band 0

#define MOD_VUFREQ_ALG0_COEFFB0_ADDR                   43

#define MOD_VUFREQ_ALG0_COEFFB0_FIXPT                  0x000000C9

#define MOD_VUFREQ_ALG0_COEFFB0_VALUE                  SIGMASTUDIOTYPE_FIXPOINT_CONVERT(2.39778213712877E-05)

#define MOD_VUFREQ_ALG0_COEFFB0_TYPE                   SIGMASTUDIOTYPE_FIXPOINT

#define MOD_VUFREQ_ALG0_COEFFB1_ADDR                   44

#define MOD_VUFREQ_ALG0_COEFFB1_FIXPT                  0x00000192

#define MOD_VUFREQ_ALG0_COEFFB1_VALUE                  SIGMASTUDIOTYPE_FIXPOINT_CONVERT(4.79556427425754E-05)

#define MOD_VUFREQ_ALG0_COEFFB1_TYPE                   SIGMASTUDIOTYPE_FIXPOINT

#define MOD_VUFREQ_ALG0_COEFFB2_ADDR                   45

#define MOD_VUFREQ_ALG0_COEFFB2_FIXPT                  0x000000C9

#define MOD_VUFREQ_ALG0_COEFFB2_VALUE                  SIGMASTUDIOTYPE_FIXPOINT_CONVERT(2.39778213712877E-05)

#define MOD_VUFREQ_ALG0_COEFFB2_TYPE                   SIGMASTUDIOTYPE_FIXPOINT

#define MOD_VUFREQ_ALG0_COEFFA1_ADDR                   46

#define MOD_VUFREQ_ALG0_COEFFA1_FIXPT                  0x00FEBCBC

#define MOD_VUFREQ_ALG0_COEFFA1_VALUE                  SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1.99013472386459)

#define MOD_VUFREQ_ALG0_COEFFA1_TYPE                   SIGMASTUDIOTYPE_FIXPOINT

#define MOD_VUFREQ_ALG0_COEFFA2_ADDR                   47

#define MOD_VUFREQ_ALG0_COEFFA2_FIXPT                  0xFF814020

#define MOD_VUFREQ_ALG0_COEFFA2_VALUE                  SIGMASTUDIOTYPE_FIXPOINT_CONVERT(-0.990230635150077)

#define MOD_VUFREQ_ALG0_COEFFA2_TYPE                   SIGMASTUDIOTYPE_FIXPOINT

==> Here Band 1

#define MOD_VUFREQ_ALG0_COEFFB0_ADDR                   49

==> But constant MOD_VUFREQ_ALG0_COEFFB0_ADDR is the same as previous band !

#define MOD_VUFREQ_ALG0_COEFFB0_FIXPT                  0x0000476D

#define MOD_VUFREQ_ALG0_COEFFB0_VALUE                  SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0.00217980628818444)

#define MOD_VUFREQ_ALG0_COEFFB0_TYPE                   SIGMASTUDIOTYPE_FIXPOINT

#define MOD_VUFREQ_ALG0_COEFFB1_ADDR                   50

#define MOD_VUFREQ_ALG0_COEFFB1_FIXPT                  0x00000000

#define MOD_VUFREQ_ALG0_COEFFB1_VALUE                  SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0)

#define MOD_VUFREQ_ALG0_COEFFB1_TYPE                   SIGMASTUDIOTYPE_FIXPOINT

#define MOD_VUFREQ_ALG0_COEFFB2_ADDR                   51

#define MOD_VUFREQ_ALG0_COEFFB2_FIXPT                  0xFFFFB893

#define MOD_VUFREQ_ALG0_COEFFB2_VALUE                  SIGMASTUDIOTYPE_FIXPOINT_CONVERT(-0.00217980628818444)

#define MOD_VUFREQ_ALG0_COEFFB2_TYPE                   SIGMASTUDIOTYPE_FIXPOINT

 

Sorry for the storm of questions ...

 

Thanks for answers !

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