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Using the PLL in the AD9510

Question asked by andre-dekker on Sep 18, 2013
Latest reply on Sep 19, 2013 by Kyle.Slightom

Dear all,

 

I want to use the PLL in the AD9510 to perform jitter cleanup on my reference clock. I have a couple of 14-bit ADC's (AD9649)

om my board, with a sample frequency of 40MHz. So I need the jitter to be below 300fs.

So I've chosen the following components for this setup, I will use an external VCXO with second order passsive loop filter.

 

The reference clock is 80MHz (CCHD-950-25-80.00) and I the VCXO is 160MHz (VFVX130-BE-160MHz),

I've read in a couple of papers that is better to go with a higher reference and VCXO clock, because you also divide the phase noise

with the R and N divider, is this a correct assumption?

 

Now I've looked on the internet for techsheets, white papers, handbooks...... But there are so many people telling

so many things on designing a PLL. I've used the ADIsimCLK1.50 to check te jitter performance and I could get

it under 300fs with the parts I mentioned above. The only thing I don't get is how do I find the correct phase detector

frequency and what are the influences if I make it higher or lower. For the simulation I choose a phase detector

frequency of 10MHz.

 

What I also don't get is how can I find the best phase margin and the bandwith for the PLL loop filter.

I've tried several values, ADIsimCLK1.50 gives a default of 10KHz bandwidth and 45 degrees of phase margin.

If I change the bandwidth you can see a change in lock time and a change in jitter performance.

Lock time for me is not so important, I can easily wait for a second when starting up the electronics. So I've

looked at the jitter performance. I've attached the phase noise plots of a bandwith of 10KHz and a bandwith of

1KHz. In both situations the phase margin is 45 degrees. If I lower the bandwith I get lower jitter, so should I

go for 1KHz bandwith? or can I make it even lower?

 

Can anyone of you please advise me on this and give a good explanation on choosing a good phase detector

frequency and phase margin and bandwith for the loop filter.

 

With kind regards,

 

Andre Dekker

 

 

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