I have a SHARC 21371 DSP connected to a FPGA via Asynchronous Memory Interface (AMI). The FPGA samples RD# and WR# signals with its internal clock, which is completely asynchronous to SDCLK. I enabled wait states and set WS to 4.
From the processors datasheet, I have two questions regarding timings:
1. I'm latching data at a fix delay after detecting a write access (i.e. not using the rising edge of WR# to latch data). So I need to know how long I have to wait after WR# goes low, until data is valid?
2. For read requests, I assert data and ACK during the same FPGA clock cycle. The datasheet specifies a minimal data setup time before RD# goes high of 2.2ns. So my question is: when releasing the ACK signal (ACK changes from low to high), when will RD# go high? i.e. what are the data to ACK setup / hold times?
My application is somewhat time critical, therefore I try to configure AMI timings as thight as possible.