I am building a custom board with DSP BF533 and Xilinx processor and trying to establish the communication between these 2 using SPORT1.
I am sending the data through xilinx part and trying to read via sport1 of BF533. I am using internal clocks. I am using early FS and I am sending the data on the rising edge of BCLK.
Here are some questions regarding this.
1. When I enable the receiver I am seeing continuous FS, BCLKs. Is this the expected operation?
2. When BF reads the data 1st time it is reporting junk data. 2nd read through 5th read it is giving the correct data. From 6th read onwards higher and lower 16bits are swapped. How to avoid this? I checked the signal on the scope. I am sending the correct data but the blackfin is reporting wrong.
Here is my initialization file
*pSPORT1_RCR1 = 0x0602;
//*pSPORT1_RCR2 = SLEN_32;
*pSPORT1_RCR2 = 0x001f;
// Sport1 transmit configuration
// Internal CLK, Internal Frame sync, MSB first
// 32-bit data
*pSPORT1_TCR1 = 0x0602;
*pSPORT1_TCR2 = 0x001f;
*pSPORT1_TCLKDIV = 0x00ff;
*pSPORT1_RCLKDIV = 0x00ff;
*pSPORT1_TFSDIV = 0x001f;
*pSPORT1_RFSDIV = 0x001f;
I am turning on the receiver by loading *pSPORT1_RCR1 = 0x0603; and after that I am reading data register.
value = *pSPORT1_RX;