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Question asked by frankd on Sep 12, 2013
Latest reply on Sep 20, 2013 by ChrisD.Rama

We are having some product issues with the AD7190.


If we don’t respond to the RDY# flag for a period of time then come back to reading the ADC we sometimes get a problem.


To try and work out why it seems to deviate from the expected operation we read back the status register and get 0xFF, which is bad on many reasons, the main one being that the datasheet states that bit[3] should always be LOW.


After doing a reset the chip works fine.


Can you provide any clues as to why this might be happenning?


We also have the CS HIGH until the RDY#  flag goes low as we have several other devices on the same SPI. We only take CS# low after we see the RDY# go LOW. The datasheet is vague at showing what this sequence would do as all examples start with CS# being LOW. Not sure if this is relevant but thought I should include anyway.


Thank you