1. We have the ADV7611 evaluation board. We have tested our EDID with an inline programmable box between our video card and the evaluation board. We get an HDMI picture out of the evaluation board.
2. The register contents of the eval board were exported and used in our design.
Remaining references our design using the ADV7611 in our design-----
3. Our design uses an oscillator to drive XTALP (1.8V, 27MHz). 27MHz is present, clean and is from a low jitter source. (probed on the back of the board, not at the ADV7611 pins) IO register 0x04 set to 0x60.
4. DVI data and clock 74.25MHz are being driven, observed with scope.
5. EDID is read correctly and stored in Windows registry, compared registry with values programmed, matches.
(Test wire on Vsync output)
No vsync when DVI is being driven.
Vsync present when DVI is off
With DVI present HDMI registers 0x51, 0x52 are 0x00, 0x00; which should be the TMDS clock frequency.
Attached txt file shows contents of ADV7611 registers. Software started at address offset 0x00 and read 256 bytes, exceeds the register space for some MAPS.
The following was found in the engineer zone.
"To use the clock oscillator, you must set the following I2C control - DPLL Map, 0xC0[7:6] to 10."
in other posts floating XTALN is only mentioned.
I strongly suspect some type of configuration problem.
It would be much appreciated if some test/register verification could be suggested.