I have a custom board with an ADAU1961 CODEC and have interfaced it to a Blackfin 533 using SPI and SPORT0. I have set up the CODEC for I2S communications based on figure 57 of the ADAU1961 data sheet i.e..
LRCLK Polarity (LRPOL - Frame begins on falling edge)
LRCLK Mode - 50% duty cycle
BCLK Polarity - Data changes on falling edge
BCLK Cycles/Audio - 48
Data Delay from LRCLK Edge (LRDEL[1:0] - Delayed from LRCLK edge by 1 BCLK
Running a simple talk through program and feeding an analogue signal into my CODEC provides data to the Blackfin via the SPORT. However, the left and right channels seem to be randomly allocated in my Blackfin buffer. Sometimes the buffer starts L,R,L,R,L,R and other times I have R,L,R,L,R,L. My buffer should be alternating samples of L,R,L,R since I set the SPORT for stereo operations RSFSE =1 and RRFST = 0.
I suspect the problem is something to do with the definition of the active bit clock and frame clock edges but I'm finding some difficulty understanding the meaning of some of the fields in the SPORT0_RCR1 and SPORT0_RCR2 registers (LARFS LRFS. Can you assist with the meaning and correct setting of the SPORT0_RCR1 and SPORT0_RCR2 register fields for I2S communications.