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Strange behavior Chip Select (CS)  AD7606

Question asked by rschoop on Sep 10, 2013
Latest reply on Oct 8, 2014 by marekm

Hello all,


I am working with the  AD7606 and also the AD7656-1 for a while   and  until now  I  had no problems.  The processor is connect to one ADC and everything works fine.


I have a new design with the AD7606 and also the AD7656-1 on the same board.  They share the same  Chip Select pin  and also the Clock  provided by the  processor.


The AD7656-1 works fine , but   the AD7606  is  not working .   After lot of probing  I  noticed that when the  probe is  connected to the  CS  the  AD7606  is  working fine   , but  when  I remove the probe  it is not working anymore.


I am thinking in the direction of  input capacitance of the ADC's  that are  in parallel that  may  brings some delay / mismatch  issues between SCLK and CS.   AD7656-1 has a  Cin of 10 pf  and  AD7606  a Cin  of  5 pF.


When the probe is connected  ,   you have to take into account in the larger input capacitance  of the probe. 


My  question is as follow  ,  according to my code   the falling edge of the CS occurs at the same time as the first rising edge of the first clock . I am clocking with 64 pulses. Because of the  input capacitance described above,   there could be some  delay  that  can cause that the  first rising edge of the SCLK  occurs after  the  CS falling edge and you will then lose the MSB.   Could this be the problem ??


I believe because of the larger Cin of the probe  that is connected to the CS pin ,  the   CS waveform is then delayed  where  the falling edge occurs after the  first rising edge of the SCLK , which than "fix" the problem. The  CS falling egde outputs the MSB and the subsequent 15 rising edges clocks the rest of the bits of the first word.   Am  I thinking right ??


Can someone shed some light on the timing relationship between the falling edge of the CS  and  the SCLK ??   Should I avoid sharing CS and SCLK pins ??


Thanks in advance,