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AD9736 SPI timing - SCLK to CSB hold time

Question asked by aerskine on Sep 9, 2013
Latest reply on Sep 9, 2013 by danf



I have two questions regarding the SPI timing in the AD9736 Datasheet, Rev A.


1. How long does CSB (Chip Select) need to be kept low after the final SCLK rising edge at the end of an SPI write transfer?
There is a specification t_DH > 5ns which defines the hold time for the data on SDIO after it has been latched by the rising edge of SCLK.

However, I couldn't find any indication of the hold time for the chip select CSB signal, either in a diagram or in the text.


2. There are contradictory statements in the datasheets regarding whether CSB can be brought high during an SPI transfer.

At the bottom left of page 36:


"CSB (Chip Select) can be raised after each sequence of 8 bits

(except the last byte) to stall the bus. The serial transfer resumes

when CSB is lowered. Stalling on nonbyte boundaries resets

the SPI."


At the top left of page 37.

"Chip select should stay low during the entire communication cycle".


Which of these statements is true?


Thanks and best regards