AnsweredAssumed Answered

AD9889B I2S audio not working

Question asked by JanGobin on Sep 6, 2013
Latest reply on Sep 19, 2013 by GuenterL

Hi All,

 

I am using an Altera Stratix4GX 530 device connected to the AD9889B chip. I am trying to get the audio up and running but unfortunately without any success.

 

Setup:

 

I have a 480p video test pattern output (running on a 27MHz pixel clock). The HDMI video is working fine.

For the audio : 48kHz Stereo, SCLK=3.072MHz, LRCLK=48kHz, MCLK=12.288MHz.

(I create these clocks with a PLL in the FPGA from the 27MHz video clock, so an integer relationship exists)

I pad the 16 bit audio data with zeroes to form 32 bit words. The 16 bit audio data that I would like to hear is a saw-tooth of about 100 Hz.

 

I set the following registers :

 

wr 0x96 <- 0x00 --clear interupts

wr 0x41 <- 0x50 --power down chip

rd  0x42 -> 0xE0

wr 0x17 <- 0x18 --csc

wr 0x3b <- 0x01 --enable csc

wr 0x15 <- 0x20 --48kHz audio; YCbCr 4:4:4 input

wr 0x16 <- 0x01 --output = YCbCr

wr 0x0C <- 0x04 --enable I2S(0), I2S format=standard (I am using 32bit per sample here, 2x32 for 1 stereo sample)

wr 0x50 <- 0x20 --enable 2 audio channels

wr 0x14 <- 0x02 --16 bit word length

wr 0x0A <- 0x01 --select I2S, Mclk inactive, Mclk ratio : 256xFs

wr 0x40 <- 0xF8 --

wr 0x44 <- 0x78

wr 0x45 <- 0x80 --AV mute disable, output format RGB

wr 0x94 <- 0xF0 --

wr 0x95 <- 0x00 --

wr 0x96 <- 0x40 --

wr 0x97 <- 0x00 --

wr 0x98 <- 0x07 --

wr 0x9C <- 0x38 --

wr 0x9D <- 0x60 --

wr 0xBB <- 0xFF --

wr 0x01 <- 0x00 --N = 6144

wr 0x02 <- 0x18

wr 0x03 <- 0x00

wr 0xAF<- 0x16 --HDMI mode

wr 0x41 <- 0x10 --power up chip

 

 

I have been comparing my register settings + general setup with other posts on this forum but can not figure out where I am going wrong.

 

Could anybody please help?

 

In Advance thx for your help

Outcomes