AnsweredAssumed Answered

Clock-to-data pair skew constraint in hdmi/dvi/tmds interface?

Question asked by economou on Sep 6, 2013
Latest reply on Sep 6, 2013 by DaveD

My understanding is that the tmds clock runs at 1/10 the datarate, and is used as a reference for clock recovery on each data pair.


If it is only used as a reference clock to a clock recovery module, I would expect that time delay between the clock pair and data pair is inconsequential, though jitter and stability are important.


Is this correct?