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Questions about SPORTs Interrupt Configuration and Processing by C, and about DMA

Question asked by nlsa001 on Sep 5, 2013
Latest reply on Oct 3, 2013 by nlsa001

Hi

 

I am using SPORT0 and SPORT0 for ADC and DAC control and sample. So far both SPORTs woke well for the ADC and DAC, but I only use polling to process the data reading from ADC and data writing to DAC.

 

Now I want to sample five analog signals and send one of them to DAC as a processing cycle, and I want to use interrupt and ISR to do this job under C. I only have experience in MCU Interrupt processing with assembly language, but not C. I read some materials (ADSP-214XX SHARC Hardware Ref and SHARC Processor Programming Ref) about interrupt processing. So far I only learned about Interrupt Enable setting in the Reg MODE1 (IRPTEN bit) and Reg IMASK for the specific interrupt source enable. I also read a code example (TWI Master.c) in which there are interrupt configuration, enabling and IRS. They look simple, but I don't how do the same processing to my application: processing SPORT1 (for receiving data) and SPORT0 (for transmitting data). Here I use the default priority setting: SPORT1 as P3I, and SPORT0 as P6I.

 

Would any one please give some me guide to the C Code writing for the interrupt processing (procedure) by some examples or some App Notes that introduces C Interrupt operation with SHARC processors? (how to configure, how to lead the IVT to the ISR, and how to start it, etc)

 

Besides, in my code (with ADSP21479) I use DMA for saving five ADC data (in SPORT1) for each of A.B channels. Following is my setting for it:

 

#define ChA_LtAddrStr 0x000B3000       //set a SRAM section for 5 Left ADC data

 

#define ChB_RtAddrStr 0x000B3001       //set a SRAM section for 5 Left ADC data

 

    *pIISP1A=ChA_LtAddrStr;    //Left ADC start Address (SPORT1A Index Register)
    *pIISP1B=ChB_RtAddrStr;    //Right ADC start Address (SPORT1B Index Register)
   
    *pIMSP1A=0x2;              //SPORT1A Modify Register
    *pIMSP1B=0x2;              //SPORT1B Modify Register
   
    *pCSP1A=0x5;               //SPORT1A Counter Register
    *pCSP1B=0x5;               //SPORT1B Counter Register

 

(I want to save five Left ADC data into 0,2,4,6,8 start from 0xB3000, and five Right ones into 1,3,5,7,9 start from 0xB3001).

 

My setting for the DMA is correct?

 

Thank you,

 

Ning

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