At the company we're now making an SDR application with the Zedboard and ad-fmcomms1-ebz. Now that Vivado 2013.2 support the Zedboard we have tried to export the reference design from XPS to Vivado. With this we encounter some problems.
In the XPS graphical Design View the axi_ad9643 is connected with the DMA trough a slave to slave bus without any master (see XPS_adc.png). This is also with the axi_ad9122 and the VDMA but than master to master without a slave. Also, the inputs adc_start_in and dma_start_in of the axi_ad9643 core are connected with the input dac_enable_in of the axi_ad9122 without an output or external port. Our question is: how and why this work. Because if you export those cores to Vivado (we followed this app note: http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_2/ug940-vivado-tutorial-embedded-design.pdf (lab5)) the s_axis_s2mm output port of the axi_ad9643 becomes an input port and it's not connectable with the input port of the dma (see exported_adc) with the axi_ad9122 core we have the same problem it becomes an output port. We have then unmapped the interface and mapped it with the right interface (for the axi_ad9643 we made it an master interface) then we can connect the cores with the DMA and VDMA, but we aren't sure this will work properly. Because we 're VHDL programmers and haven't much experience with Verilog.
So is there a proper solution for our problem? Or have Analog Devices or somebody else already exported it to Vivado? And are there vhd files of those 2 cores?