I'm trying to use the ADCMP553 comparator to capture and hold a fast trigger signal. I would like to somehow feedback the output of the comparator to the latch so that when the comparator goes HIGH it stays high. I would use a signal from an FPGA to reset the latch. Has anyone done something like this or is there any app note somewhere?
I've attached a schematic of one way I could imagine doing this except that the latch signals are not LVPECL compliant. (Also it is just half of the differential pair.) In this scheme, the Trigger Reset pin would be tri-stated until the trigger was read into the FPGA. At this point, the Trigger Reset pin would be pulled Low (or High depending on which half of the differential pair it was connected to) to reset the comparator to compare mode.
Thanks for any help or ideas,