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FrameSync synchronisation with PCG

Question asked by Hfuhrhurr on Aug 30, 2013
Latest reply on Sep 30, 2013 by MaheshN

Hi all,

 

I am having troubles in synchronising to FS signals that I am generating with the PCG.

The situation:

I have a Sharc 21469 connected to a TI codec with TDM8 and to an AES source.

The DSP is driven by a 12.288MHz oszillator x 32 -> 393.216 MHz

 

PCGA is generating a 24.576MHz MCLK

PCGB is generating a 12.288 BCLK and a 48kHz FS pulse for the Codec

PCGC is generating a 3.072MHz BCLK and a 48kHz FS signal for AES

 

Now, the FS starts should be aligned, so that when the Codec DMA transfers are done, also the AES signals are there and I can start processing them. Therefore I want to synchronise PCGC to PCGB to have the frame syncs aligned. I am not absolutely sure, if that is the right way or if I am doing anything wrong.

 

This is my code (apologies, how it looks, but I can't convince the *$%$§ editor here that my code is not a table.)

 

#define SAMPLERATE    48000
#define CLKINFREQ     12288000
#define CLKMULTIPLIER 32
#define CPUCLK        CLKINFREQ * CLKMULTIPLIER
#define PCLK          CPUCLK / 2

 

#define CODEC_MCLK       (SAMPLERATE * 512) // = 24576000
#define CODEC_BCLK       (SAMPLERATE * 256) // = 12288000
#define CODEC_FS_DIV     (PCLK / SAMPLERATE)
#define CODEC_MCLK_DIV   (PCLK / CODEC_MCLK)
#define CODEC_BCLK_DIV   (PCLK / CODEC_BCLK)
#define CODEC_FS_PHASE    8
#define CODEC_FS_PW      16

 

#define AES_BCLK        (SAMPLERATE *  64) // =  3072000
#define AES_BCLK_DIV    (PCLK / AES_BCLK)
#define AES_FS_DIV      (PCLK / SAMPLERATE)
#define AES_FS_PHASE    1

 

 

 


*pPCG_SYNC1 = CLKA_SOURCE_IOP | FSA_SOURCE_IOP | CLKB_SOURCE_IOP | FSB_SOURCE_IOP

| CLKB_SYNC | FSB_SYNC ;

 


//CLK Divisor & FS Phase 0-9

*pPCG_CTLA1 = CODEC_MCLK_DIV;

 


//FS not used, Enable Clock

*pPCG_CTLA0 = ENCLKA;

 


//CLK Divisor & FS Phase

// If the phase shift is one, the frame sync output transitions

// one input clock period ahead of the clock transition

*pPCG_CTLB1 = CODEC_BCLK_DIV | ((CODEC_FS_PHASE & 0x3FF) << 20);

 


//FS Divisor = 4 & FS Phase 20-29 =0, Enable Clock

*pPCG_CTLB0 = ENCLKB | ENFSB | ((CODEC_FS_PHASE >> 10) <<20) | CODEC_FS_DIV; 

 

 


*pPCG_PW1 = (CODEC_FS_PW << 16);

 

 


SRU (PCG_CLKA_O, PCG_SYNC_CLKB_I);

SRU (PCG_FSB_O, PCG_SYNC_CLKC_I);

 


*pPCG_SYNC2 = CLKC_SOURCE_IOP | FSC_SOURCE_IOP | CLKC_SYNC | FSC_SYNC;

 


Delay(10); // used to experiment with delays between activating the clocks

//FS Divisor & FS Phase 20-29

*pPCG_CTLC0 = ENCLKC | ENFSC | ((AES_FS_PHASE >> 10) <<20) | AES_FS_DIV; 

 


//CLK Divisor & FS Phase 0-9

*pPCG_CTLC1 = AES_BCLK_DIV | ((AES_FS_PHASE & 0x3FF) << 20);

 

 

 

 

May somebody have a look at this? Thanks in advance,

 

Rainer

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