Two days ago I posted a question about TWI. So far the issue still exist. I use uC as TWI Master and DSP (ADSP21479) as the Slave. In my test code I just see if uC could send a data and if it could be received by DSP. Through the scope, I only can see the ADDRESS from uC and ACK from DSP and then the transfer stopped because of the Low TWI CLK happened. I don't know which side makes the CLK line low, and how to release the CLK Line.
When I debugged the codes for both processors, I used their emulators (the ADSP uses ADZS-USB-ICE) in a same PC and they have to work at same time. The test procedure is like this: I first run uC code for TWI Master initiation and then halted it, then I turned the ADSP for running its System Clock and TWI Slave initiation and then polling the interrupt sources about TWI, when it kept polling, I turned to uC and let it run for sending the Slave ADDRESS and then if the ADDRESS is ACKed by DSP, uC would send a data. then I only see the ADDRESS from uC and ACK from, and the DSP doesn't seem to latch any interrupt sources about the TWI.
In uC's datasheet, it introduces about Time Out for TWI processing, but I disabled the function at configuration, I don't know if DSP has the same processing, and if my debugging method (use two emulator in the same PC) could damage the TWI operation.
Attached is my code for the test.
Would any one please answer my questions or need more information about my test?
Thanks a lot,