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Level of SYNC_CLK of AD9915

Question asked by hanseyo on Aug 29, 2013
Latest reply on Sep 11, 2013 by DSB


At first, I'd like to say thanks for kill answer of my past questions specially to DSB.

But I still have a question.

As I know from data sheet, SYNC_CLK output of AD9915 is digital port.

But when checked using an oscilloscope, level of SYNC_CLK was smaller according to increasing of reference clock.

In case of using 2.5GHz reference clock, width of swing of SYNC_CLK was reduced enough not to recognize by FPGA.

If the SYNC_CLK is digital port didn't the width of swing of SYNC_CLK have to be constant?