Good morning. I have a customer experiencing a problem with a SPI bus that is going through ADG3304s for level translation. The bus works fine before they activate the power domain which contains the ADG3304s at which point the bus get very messy and even starts oscillating uncontrollably at times. They have the following questions:
1) They have seen different results when they remove the ADG3304s completely and when we tri-state it. What is the resistance of I/Os
during the high-impedance state?
Rich's Note: I have sent them information on the output impedance (6k +/-30%) during operation contained in another post. I am
assuming that the impedance should be on the order of megaohms but wanted to confirm for the customer.
2) Their application has two ADG3304s back to back with a long trace in between (please see the attached block diagram). Is this an
acceptable use case?